The invention relates generally to MicroElectroMechanical Systems (MEMS). Specifically, this invention provides a technique for microfabricating structures using Silicon-On-Insulator (SOI) material.
The rapidly emerging field of MicroElectroMechanical Systems (MEMS) has penetrated a wide array of applications, in areas as diverse as automotives, inertial guidance and navigation, microoptics, chemical and biological sensing, and biomedical engineering. Use of Silicon-On-Insulator (SOI) material is rapidly expanding in both microelectronic and MEMS applications, because of increasing demand for tight limits on wafer specifications, the low cost of SOI, its process flexibility, radiation hardness and compatibility with high-level integration. Significant benefits may be realized by utilizing SOI material to fabricate inertial sensors, chemical and biological sensors, optoelectronic devices, and a wide range of mechanical structures such as microfluidic and microoptical components and systems. In spite of its many advantages, however, use of SOI wafers to build MEMS devices is not widespread, largely because of difficulties in processing the material.
Prior methods for fabricating MEMS devices using a bonded handle wafer include the dissolved wafer process, in which silicon is bonded to glass and the silicon is dissolved away to reveal an etch-stop layer. This etch-stop layer typically comprises a heavily-doped boron-diffused or boron-doped epitaxial layer, but may also consist of a SiGe alloy layer. However, methods that involve the use of a heavily-boron-doped etch stop suffer in several respects, including poor process control, high defect densities, limitations on ultimate thickness of devices, and incompatibility with microelectronic device integration. Insertion of a SiGe alloy layer resolves several of these limitations, but that method suffers from relatively low deposition rates and material property issues. SOI micromachining has demonstrated that a limited number of device types may be successfully constructed, but the build quality is lacking and many design constraints exist.
The principal constraint involves the problems encountered when performing deep reactive-ion-etching (RIE) of the silicon device layer on top of the oxide interlayer; the RIE process tends to attack the underside of the silicon device layer due to RIE lag, non-uniformity and other effects. Steps have been taken by RIE equipment vendors to resolve this problem, and such methods have mitigated these etch effects. However, these solutions require that the RIE process be conducted when the silicon device layer is in intimate contact with the oxide interlayer everywhere, otherwise underside attack of the silicon device layer still occurs.
This requirement has led to the development of alternative SOI processes. However, these alternative processes encounter stringent design rules related to pressure differentials across the thin oxide interlayer. Survival of the oxide interlayer is important for the success of alternative SOI processes, but no solution to this problem has previously been proposed.
Thus, there is a need in the art for a method that relieves the constraints for SOI processing.
The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) material. One first obtains a Silicon-On-Insulator (SOI) wafer, which has (i) a handle layer, (ii) a a dielectric layer, and (iii) a device layer. A mesa etch has been made on the device layer of the SOI wafer and a structural etch has been made on the dielectric layer of the SOI wafer. One then obtains a substrate (such as glass or silicon), where a pattern has been etched onto the substrate. The SOI wafer and the substrate are bonded together. Then the handle layer of the SOI wafer is removed, followed by the dielectric layer of the SOI wafer.
The method of the invention provides (1) the ability to micromachine devices on SOI substrates without design constraints for structure spacing, etch gaps, oxide thickness or other features, and (2) a flexibility for handle wafer type and bonding process. This invention also addresses several of the previous barriers to general use of SOI material for MEMS and associated applications. First, the invention enables the use of SOI wafers to build a wide array of device types that were previously only feasible using standard boron etch stop technology. Second, the method allows for the use of RIE etch technology to produce high-quality structures on devices bonded everywhere to a silicon dioxide buried layer. Third, the invention relieves all of the design constraints previously required for SOI structures, including the spacing between structural elements, spacing between the device and the edge of the die, and special requirements for atmospheric conditions during bonding of SOI wafers to handle wafers.
The invention also provides intermediate structures in the general fabrication method. The intermediate structures are mechanically stable, though they contain internal cavities formed by the etched SOI wafer and the substrate. The cavities can be of various shapes and sizes.
In one embodiment, the intermediate structure have an access port in the substrate. The access port provides mechanical stability for the structure. Accordingly, the intermediate structures can be made using components with arbitrary thickness and arbitrary doping.
The invention further provides a method for making an accelerometer, using the methods of the invention.